1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method therefor, and more specifically to multilayer wiring in a semiconductor device using an acetylene film and a manufacturing method therefor.
2. Description of Related Art
With advancements in the level of integration of semiconductor devices, there has been an increased demands with respect to multilayer wiring. In multilayer wiring, because of the importance of covering steps between wiring layers and interlayer insulating films, and flatness of interlayer insulating films, electrically conductive polymers, such as linear eutectic conjugated polymers are attracting attention.
Of such linear conjugated eutectic polymers, the characteristics of polyacetylene ((CH)x) is particularly suited to semiconductor devices. Polyacetylene is a linear polymer having alternating C--C and C.dbd.C bonds, .pi. electrons which do not contribute to these bonds (being in a direction that is perpendicular to the linear bonding) being formed in a eutectic system, so that they have the possibility of contributing to electrical conductivity.
A polyacetylene film formed by a polymerization process of acethylen ((CH)2) utilizing a Ziegler-Natta catalyst or a polyacetylene film formed by plasma polymerization of acetylene is usually an insulating film.
While the electrical conductivity of an insulating polyacetylene film is in the range of approximately 10.sup.-9 to 10.sup.-8 S/cm, by doping an insulating polyacetylene film to several mol % with impurities (for example arsenic hexafluoride (AsF.sub.6) or iodine (I.sub.2)), it is possible to obtain an electrically conductive polyacetylene film having an electrical conductivity ranging from the order of 10.sup.3 S/cm or so to a maximum of 10.sup.5 S/cm or so (approximately the same as metals such as copper or silver).
By using the above-noted characteristics of a polyacetylene film, by selectively doping an insulating polyacetylene film over a prescribed region, it is possible to form an electrically conductive wiring region over just that region.
Additionally, if the polyacetylene region that remains as an insulating region is left as is without removing it, it is possible to avoid problems related to the ability to properly cover the steps formed on the top surface of the polyacetylene film, which includes the wiring layer, using an insulating film.
Further, the problem which is caused by covering ability over the steps formed by upper wiring layer formed on upper surface of an insulating film, can also be removed.
Because of this advantage, the application of multilayer wiring made from a polyacetylene film in semiconductor devices has been indicated in the past. For example, in Japanese Unexamined Patent Publication (KOKAI) No. 58-48941 there is disclosed two-layer wiring which uses a three-layer polyacetylene film, and in Japanese Examined Patent Application publication H2-19973 (Japanese Unexamined Patent Publication (KOKAI) No. 58-48942), there is disclosed two-layer wiring which includes two-layer aluminum wiring and a two-layer polyacetylene film.
Referring to FIG. 8, which shows a schematic representation of a semiconductor device, the multilayer wiring in the semiconductor device as disclosed in the above-noted Japanese Unexamined Patent Publication (KOKAI) No. 58-48491 (hereinafter referred to as the first prior art example) is as follows. The surface of the semiconductor substrate 301 is covered by a silicon oxide film 302 which has a flat upper surface.
Onto the upper surface of this silicon oxide film 302 are laminated an insulating first polyacetylene film 311, an insulating second polyacetylene film 321, and then an insulting third polyacetylene film 331.
Over a first prescribed region of the polyacetylene film 311 is provided a first wiring layer 311a which is converted so as to be electrically conductive, and over a second prescribed region of the polyacetylene film 331 is provided a second wiring layer 331a which is converted so as to be electrically conductive. The wiring layer 331a traverses laterally across the wiring layer 311a, via the polyacetylene film 321.
In the above-noted first prior art example, the upper surface of the wiring layer 311a and the upper surface of the polyacetylene film 311 are coplanar flat surfaces.
For this reason, the polyacetylene film 321 which serves as an interlayer insulating film also has a flat upper surface, this presenting no problem of covering a step or the like with the respect to the first wiring layer 311a.
Additionally, because the second wiring layer 331a also provided on the upper surface of the polyacetylene film 321, there is no problem in covering a step at the second wiring layer 331a as well.
Referring to FIG. 9, which shows a schematic representation of a semiconductor device, the multilayer wiring in the semiconductor device as disclosed in the above-noted Japanese Examined Patent Publication H2-19973 (hereinafter referred to as the second prior art example) is as follows.
Over a device isolation region of the surface of a P-type silicon substrate 401 a field oxide film 402 is provided, over a device region of the surface of the P-type silicon substrate 401 a gate electrode 403 is formed with an intervening gate oxide film 402A, and over the surface of a device region of the surface of the P-type silicon substrate 401 is provided an N.sup.+ -type diffusion layer 404 which serves as a source-drain region which is self-aligning to the field oxide film 402 and gate electrode 403.
Additionally, on the surface of these N.sup.+ type diffusion region 404 is provided a platinum silicide layer 404A. An n-channel MOS transistor provided on the P-type silicon substrate 401 which includes the field oxide film 402 is covered by the insulating first polyacetylene film 411.
By selectively converting part of the polyacetylene film 411 that directly covers the platinum silicide film 404A so as to be electrically conductive, a first contact plug 411a is formed. Because a first aluminum wire 417 which is provided on the surface of the polyacetylene film 411 directly covers the upper end of the contact plug 411a, an electrical connection is made to the N.sup.+ type diffusion layer 404.
The surface of the polyacetylene film 411, including the aluminum wiring 417, is covered by an insulating second polyacetylene film 421. By selectively converting part of the polyacetylene film 421 that directly covers the aluminum wiring 417 so as to be electrically conductive, a second contact plug 421a is formed. Because a second aluminum wire 427 which is provided on the surface of the polyacetylene film 421 directly covers the upper end of the contact plug 421a, an electrical connection is made to the aluminum wire 417.
In the above-noted second prior art example, the contact plugs 411a and 421a, which are formed by conversion of prescribed regions of the insulating polyacetylene films 411 and 421 so as to be conductive, each function as a wiring layer that serves as a contact plug but it does not serve as a wiring layer.
Although the upper surface of the polyacetylene film 411, including the upper surface of the contact plug 411a, while not being flat, is smooth and does not have a step, a problem related to the ability to cover a step in the first aluminum wire 417 is avoided.
Although there exists a step because of the first aluminum wire 417, because of the method of manufacturing, there is no problem occurring related to the ability to cover a step in the second polyacetylene film 421 which covers the first polyacetylene film 411, including these aluminum wires 417.
Also, because the surface of the polyacetylene film 421 as well, including the second contact plug 421a is also not flat, but rather is smooth and does not have a step, in the same manner as the first aluminum wiring 417, a problem related to the ability to cover a step in the second aluminum wiring 427 is also avoided.
In the above-described first prior art example, the first and second prescribed regions of the insulating first and third polyacetylene films are selectively converted so as to be electrically conductive, thereby forming the first and second electrically conductive wiring layers. However, the insulating second polyacetylene film (which is provided between the insulating first and third polyacetylene films) and which serves as an interlayer insulating film between the first and second wiring layers does not have a via hole or the like provided in it for the purpose of connection to these first and second wiring layers.
In a structure such as this, because the first wiring layer and the second polyacetylene film are made of the same material, it is difficult to form a via hole in the second polyacetylene film which reaches the first wiring layer without causing a problem with respect to the first wiring layer (this being the first problem with the first prior art example).
Additionally, in forming a second wiring layer by selectively doping a second prescribed region of the third polyacetylene film with an impurity, because the second (and first) polyacetylene film does not act as a stopper for this impurity used in the doping process, it is difficult to form the second wiring layer in a manner that is stopped inside the third polyacetylene film (this being the second problem with the first prior art example).
In the above-noted second prior art example, the insulating first and second polyacetylene film each function as interlayer insulation films, prescribed regions of these polyacetylene films being selectively converted so as to be electrically conductive, thereby forming the first and second contact plugs.
Because of this, the above-noted first problem in the first prior art example, related to connection between the upper wiring layer and the lower wiring layer, is solved. Additionally, in the second prior art example, when for example the second prescribed region of the second polyacetylene film is selectively doped with an impurity, because the first aluminum wiring functions are a stopper, the above-noted second problem in the first prior art example is also solved.
However, in the above-noted second prior art example, if for example a prescribed region of the insulating second polyacetylene film is selectively converted so as to be electrically conductive, thereby forming a wiring layer, a problem similar to the above-noted second problem of the first prior art example arises, so that while it is possible to form a contact plug in the second polyacetylene film of the second prior art example, the formation of a wiring layer is difficult. Additionally, in the second prior art example, although the upper surface of the second polyacetylene film, which covers the first aluminum wiring is smooth, it has unevenness and is not flat.
Because of this, no problem arises with coverage at the time of formation of the aluminum film for the purpose of forming the second aluminum wiring layer.
However, in the photolithography process for forming the second aluminum wiring layer, a problem arises with regard to depth of focus that is attributable to the unevenness of the upper surface of this second polyacetylene film, so that it is not easy for patterning the second aluminum wiring. That is, the second prior art example does not take sufficient advantage of the benefit of the polyacetylene film.
In view of the above-described problems occurring in the prior art, an object of the present invention is to provide multilayer wiring formed of flat laminations by sufficiently exploiting the advantage of a polyacetylene film, and a manufacturing method therefor.